FIG. 1 is a schematic representation of a typical memory device 10. The memory device 10 comprises an array of cells 5AA, 5BB, 5BA, etc. Each cell is used to store one bit of data. Each row of cells in the array is linked by a word line 8A, 8B, etc., while each column of cells in the array is linked by a bit line, 12A, 12B, 12C, etc. Any given cell can therefore be uniquely specified by a combination of the appropriate word line 8 and bit line 12. For example, as shown in FIG. 1, cell 5EF can be accessed by the combination of word line 8E and bit line 12F. An X-decoder 35 (also referred to as a row decoder) is used to select a word line 8, while a Y-decoder 25 (also referred to as a column decoder) is used to select a bit line 12, both dependent upon the specified address of a memory operation.
The memory device 10 further includes a sense amplifier 20 connected to each bit line. The sense amplifier is used to read data from or write data to a desired memory cell 5, in accordance with the selected word line 8 and bit line 12. Note that although sense amplifier 20 is shown in FIG. 1 as a single block, it may be implemented as a separate sense amplifier per bit line.
The memory device 10 of FIG. 1 comprises an 8×8 cell storage array, but it will be appreciated that most commercial memory devices incorporate a much larger number of cells. In addition, the number of rows of cells in the array will often be different from the number of columns.
The implementation of an individual memory cell 5 within memory device 10 depends upon the particular type of memory device. For example, in static random access memory (SRAM), each memory cell 5 may comprise a pair of cross-coupled inverters. In dynamic random access memory (DRAM) each cell may comprise a single access transistor and storage capacitor. Other forms of memory device, such as read only memory (ROM) and non-volatile storage (e.g. flash memory) are known in the art, and have a corresponding form of memory cell 5. Memory device 10 is generally formed from a semiconductor material, although an analogous architecture could potentially also be used with other materials, such as organic polymers.
A memory access operation for memory device 10 involves asserting a word line 8 and a bit line 12 corresponding to the cell 5 that is desired to be accessed. The word line and bit line are de-asserted when the memory operation to the desired cell has completed. Note that the precise timing of the assertion and de-assertion of the word line 8 and bit line 12 depends upon the type of memory cell 5, and may not occur simultaneously. For example, a word line for a cell may be asserted before the corresponding bit line. Once the memory operation for a first cell has completed, and the word line and bit line have been de-asserted, a second memory cell can now be accessed by asserting a different word line and bit line as appropriate for the second memory cell.
The X-decoder 35 is used to assert and to de-assert a word line 8, and the Y-decoder 25 is used to assert and to de-assert a bit line 12. However, it can take a significant time for the assertion of a word line to propagate through the array. For example, if X-decoder 35 asserts word line 8F, then cells at the head of the word line (i.e. relatively near to X-decoder 35, such as cell 5FA) are turned on sooner than cells at the tail of the word line (i.e. relatively far from X-decoder 35, such as cell 5FH). There is a similar propagation delay associated with de-asserting a word line 8. Accordingly, there is a skew in timing across a word line 8 from the bit lines 12 at the head of the word line to the bit lines at the tail of the word line.
Two very important operating characteristics of a memory device are its storage capacity and its speed of operation. One limitation on the speed of a memory device is the time taken to switch from one word line to another—in other words, the time taken to de-assert a word line for a first memory cell, and then to assert a word line for a second memory cell. For example, in SRAM, the timing of a write operation is dominated by this word line delay.
A major component in the word line delay is the propagation time or skew along the length of the word line. One way to reduce the word line delay is therefore to limit the number of columns (bit lines) in a memory device array, since the fewer cells there are on a word line, the more quickly the word line switch will complete. However, restricting the length of a word line by reducing the number of cells limits the capacity of the memory device 10.
Some memory devices have tried to combat the word line delay problem by having multiple arrays in the storage device. Such devices can be considered as adding an extra dimension to the storage device, in that any given cell is now specified by a combination of bit, word, and also array (rather than just by bit and word as for the device 10 of FIG. 1). This then allows a memory device to have increased capacity without increasing the length of the word line, thereby preserving memory access speed. However, having multiple arrays in this fashion significantly increases the cost and complexity of a memory device compared to the simple array shown in FIG. 1.
US 2003/0210583 describes a hybrid memory array having multiple row decoders associated with just a single column decoder. The use of multiple row decoders allows the use of shorter word lines—i.e. each memory cell is relatively close to the head of its respective word line (segment). Although this approach can be regarded as simpler than having multiple separate memory arrays, in that now there is only a single column decoder, the architecture is again more complicated and costly than the simple array shown in FIG. 1.
US 2004/0003195 describes a memory device having a small capacity high-speed random access memory and a large capacity low-speed random access memory. It is assumed that a block of data corresponding to one or more whole words (for example a page of memory) is to be stored in such a device. A first, relatively small portion of the data is stored in the small capacity high-speed memory array, while the remaining (larger) portion is stored in the large capacity low-speed memory array. When this data is read, both memory arrays are accessed at the same time. The first portion of the data is available quickly from the high-speed small capacity memory, and by the time that this first portion of the data has been read, the remaining portion of the data is now available from the large capacity, low-speed device. Although such an approach can help to compensate for word line delay, the use of two different memory arrays once again increases the cost and complexity of the device compared to the simple array of FIG. 1.
FIGS. 2 and 3 illustrate a problem that can arise from the skewed timing of a word line switch such as described above. In particular, the problem may arise if the switching between word lines does not fully allow time for a word line assertion or de-assertion signal to propagate along the full length of the word line.
FIG. 2 depicts two (arbitrary) word lines 8N, 8J and two (arbitrary) bit lines 12K and 12Y, plus associated memory cells 5NY, 5NX, 5NK, 5NJ, 5JY, 5JX, 5JK, and 5JJ. Note that for clarity, the remaining bit lines, word lines, and memory cells of device 10 are omitted from FIG. 2. It is assumed that there are a relatively large number of bit lines between bit line 12K and X-decoder 35, and further a relatively large number of bit lines between bit line 12K and bit line 12Y. Hence there may be a significant timing skew between the word line signal from X-decoder 35 and the word line signal at bit line 12K, and a further significant timing skew between the word line signal at bit line 12K and the word line signal at bit line 12Y.
We assume that device 10 has just finished accessing memory cell 5NY and now wants to access memory cell 5JK. This involves de-asserting word line 8N and asserting word line 8J. FIG. 3 illustrates the sense path for cell 5JK once word line 8J is asserted, as shown by the dotted arrows denoted S1, S2, S3, S4, and S5. If cell 5JK is accessed before word line 8N has been fully de-asserted at the previously accessed cell 5NY, then a leak path exists, as shown in FIG. 3 by the dotted arrows L1, L2, L3, L4 and L5 (corresponding to the previous sense path for cell 5NY). This leakage can interfere with or mask the signal from/to the cell 5JK that is now being accessed.
It will be appreciated therefore that word line switching delays in memory devices reduce memory access speed, and can also lead to the risk of leakage. However, previous attempts to combat such problems have generally required increased complexity and cost of the memory device.